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?2015 integrated device technology, inc. july 2015 dsc 3741/12 1 high-speed 3.3v 1k x 8 dual-port static ram IDT71V30S/l features high-speed access ? commercial: 25/35/55ns (max.) ? industrial 35ns (max.) low-power operation ? IDT71V30S ? active: 375mw (typ.) ? standby: 5mw (typ.) ? idt71v30l ? active: 375mw (typ.) ? standby: 1mw (typ.) functional block diagram notes: 1. idt71v30: busy outputs are non-tristatable push-pulls. 2. int outputs are non-tristable push-pull output structure. on-chip port arbitration logic interrupt flags for port-to-port communication fully asynchronous operation from either port battery backup operation, 2v data retention (l only) ttl-compatible, single 3.3v 0.3v power supply industrial temperature range (-40 o c to +85 o c) is available for selected speeds green parts available, see ordering information i/o control address decoder memory array arbitration and interrupt logic address decoder i/o control r/ w l ce l oe l busy l a 9l a 0l 3741 drw 01 i/o 0l -i/o 7l ce l oe l r/ w l int l busy r i/o 0r -i/o 7r a 9r a 0r int r ce r oe r (2) (1) (1) (2) r/ w r ce r oe r 10 10 r/ w r
6.42 IDT71V30S/l high-speed 1k x 8 dual-port static ram with interrupts industrial and commercial temperature ranges 2 notes: 1. all v cc pins must be connected to the power supply. 2. all gnd pins must be connected to the ground supply. 3. package body is approximately 10mm x 10mm x 1.4mm. 4. this package code is used to reference the package diagram. 5. this text does not indicate the orientation of the actual part-marking. pin configurations (1,2,3) description the idt71v30 is a high-speed 1k x 8 dual-port static ram. the idt71v30 is designed to be used as a stand-alone 8-bit dual-port sram. both devices provide two independent ports with separate control, address, and i/o pins that permit independent, asynchronous access for reads or writes to any location in memory. an automatic power down feature, controlled by ce , permits the on chip circuitry of each port to enter a very low standby power mode. fabricated using cmos high-performance technology, these de- vices typically operate on only 375mw of power. low-power (l) ver- sions offer battery backup data retention capability, with each dual- port typically consuming 200w from a 2v battery. the idt71v30 devices are packaged in 64-pin stqfps. index idt71v30tf pp64 (4) 64-pin stqfp top view (5) 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 46 45 44 43 42 41 40 39 38 37 36 35 34 47 48 33 1 7 1 8 1 9 2 0 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 4 9 5 0 5 1 5 2 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 6 4 i/o 6r n/c a 0r a 1r a 2r a 3r a 4r a 5r a 6r a 7r a 8r a 9r i/o 7r oe r n/c n/c i/o 2l a 0l oe l a 1l a 2l a 3l a 4l a 5l a 6l a 7l a 8l a 9l i/o 0l i/o 1l n/c n/c 3741 drw 03 n / c n / c n / c i n t l b u s y l r / w l c e l v c c v c c c e r r / w r b u s y r i n t r n / c n / c n / c i / o 3 l n / c i / o 4 l i / o 5 l i / o 6 l i / o 7 l n / c g n d g n d i / o 0 r i / o 1 r i / o 2 r i / o 3 r n / c i / o 4 r i / o 5 r
6.42 IDT71V30S/l high-speed 1k x 8 dual-port static ram with interrupts industrial and commercial temperature ranges 3 absolute maximum ratings (1) dc electrical characteristics over the operating temperature and supply voltage range (v cc = 3.3v 0.3v) notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v term must not exceed vcc + 0.3v for more than 25% of the cycle time or 10ns maximum, and is limited to < 20ma for the period of v term > vcc + 0.3v. 3. this is the absolute maximum junction temperature for the device. no dc bias. note: 1. at vcc < 2.0v input leakages are undefined. supply currentv in > v cc -0.2v or < 0.2v capacitance (1) (t a = +25 o c, f=1.0mhz) notes: 1. this parameter is determined by device characterization but is not production tested. 2. 3dv references the interpolated capacitance when the input and output signals switch from 0v to 3v or from 3v to 0v. symbol rating com'l & ind unit v term (2) terminal voltage with respect to gnd -0.5 to +4.60 v t bias temperature under bias -55 to +125 o c t stg storage temperature -65 to +150 o c t jn (3) junction temperature +150 o c i out dc output current 50 ma 3741 tbl 01 symbol parameter conditions (2) max. unit c in input capacitance v in = 3dv 9 pf c out (3) output capacitance v out = 3dv 10 pf 3741 tbl 04 symbol parameter test conditions 71v30s 71v30l unit min. max. min. max. |i li | input leakage current (1) v cc = 3.6v, v in = 0v to v cc ___ 10 ___ 5a |i lo | output leakage current ce = v ih , v out = 0v to v cc ___ 10 ___ 5a v ol output low voltage (i/o 0 -i/o 7 ) i ol = 4ma ___ 0.4 ___ 0.4 v v oh output high voltage i oh = -4ma 2.4 ___ 2.4 ___ v 3741 tbl 05 recommended dc operating conditions maximum operating temperature and supply voltage (1,2) note: 1. v il (min.) = -1.5v for pulse width less than 20ns. notes: 1. this is the parameter t a . this is the "instant on" case temperature. 2. industrial temperature: for specific speeds, packages and powers, contact your sales office. symbol parameter min. typ. max. unit v cc supply voltage 3.0 3.3 3.6 v gnd ground 0 0 0 v v ih input high voltage 2.0 ____ v cc + 0.3v v v il input low voltage -0.3 (1) ____ 0.8 v 3741 tbl 02 grade ambient temperature gnd vcc commercial 0 o c to +70 o c0v 3.3v + 0.3 industrial -40 o c to +85 o c0v 3.3v + 0.3 3741 tbl 03
6.42 IDT71V30S/l high-speed 1k x 8 dual-port static ram with interrupts industrial and commercial temperature ranges 4 notes: 1. v cc = 2v, t a = +25c, and is not production tested. 2. t rc = read cycle time. 3. this parameter is guaranteed by device characterization but not production tested. data retention characteristics (l version only) dc electrical characteristics over the operating temperature and supply voltage range (1,6,7) (v cc = 3.3v 0.3v) notes: 1. 'x' in part number indicates power rating (s or l) 2. v cc = 3.3v, t a = +25c, and are not production tested. i ccdc = 70ma (typ.) 3. at f = f max , address and control lines (except output enable) are cycling at the maximum frequency read cycle of 1/t rc. 4. f = 0 means no address or control lines change. 5. port "a" may be either left or right port. port "b" is the opposite from port "a". 6. refer to chip enable truth table i. 7. industrial temperature: for specific speeds, packages and powers contact your sales office. symbol parameter test condition 71v30l unit min. typ. (1) max. v dr v cc for data retention 2.0 ____ ____ v i ccdr data retention current v cc = 2 v, ce > v cc -0.2v ind. ____ 100 1000 a com'l. ____ 100 500 t cdr (3) chip deselect to data retention time v in > v cc -0.2v or v in < 0.2v 0 ____ ____ ns t r (3) operation recovery time t rc (2) ____ ____ ns 3741 tbl 07 symbol parameter test condition version 71v30x25 com'l only 71v30x35 com'l & ind 71v30x55 com'l only unit typ. (2) max. typ. (2) max. typ. (2) max. i cc dynamic operating current (both ports active) ce l and ce r = v il , outputs disabled f = f max (3) com'l s l 75 75 150 120 75 75 145 115 75 75 135 105 ma ind s l ___ ___ ___ ___ ___ 75 ___ 145 ___ ___ ___ ___ i sb1 standby current (both ports - ttl level inputs) ce l and ce r = v il , f = f max (3) com'l s l 20 20 50 35 20 20 50 35 20 20 50 35 ma ind s l ___ ___ ___ ___ ___ 20 ___ 50 ___ ___ ___ ___ i sb2 standby current (one port - ttl level inputs) ce "a" = v il and ce "b" = v ih (5) active port outputs disabled, f=f max (3) com'l s l 30 30 105 75 30 30 100 70 30 30 90 60 ma ind s l ___ ___ ___ ___ ___ 30 ___ 100 ___ ___ ___ ___ i sb3 full standby current (both ports - cmos level inputs) ce l and ce r > v cc - 0.2v v in > v cc - 0.2v or v in < 0.2v, f = 0 (4) com'l s l 1.0 0.2 5.0 3.0 1.0 0.2 5.0 3.0 1.0 0.2 5.0 3.0 ma ind s l ___ ___ ___ ___ ___ 1.0 ___ 5.0 ___ ___ ___ ___ i sb4 full standby current (one port - cmos level inputs) ce "a" < 0.2v and ce "b" > v cc - 0.2v (5) v in > v cc - 0.2v or v in < 0.2v active port outputs disabled f=f max (3) com'l s l 30 30 90 75 30 30 85 70 30 30 75 60 ma ind s l ___ ___ ___ ___ ___ 30 ___ 85 ___ ___ ___ ___ 3741 tbl 06
6.42 IDT71V30S/l high-speed 1k x 8 dual-port static ram with interrupts industrial and commercial temperature ranges 5 ac test conditions data retention waveform notes: 1. transition is measured 0mv from low- or high-impedance voltage with output test load (figure 2). 2. this parameter is guaranteed by device characterization, but is not production tested. 3. 'x' in part number indicates power rating (s or l). 4. industrial temperature: for specific speeds, packages and power contact your sales office. figure 2. output test load (for t hz , t lz , t wz and t ow ) * including scope and jig. figure 1. ac output test load ac electrical characteristics over the operating temperature and supply voltage range (3,4) input pulse levels input rise/fall times input timing reference levels output reference levels output load gnd to 3.0v 3ns max. 1.5v 1.5v figures 1 and 2 3741 tbl 08 v cc ce 3.0v 3.0v data retention mode t cdr v ih v ih v dr v dr 2.0v 3741 drw 04 t r , 590 ? 30pf 435 ? data out 590 ? 435 ? 5pf data out 3741 drw 05 3.3v 3.3v busy int 71v30x25 com'l only 71v30x35 com'l & ind 71v30x55 com'l only unit symbol parameter min.max.min.max.min.max. read cycle t rc read cycle time 25 ____ 35 ____ 55 ____ ns t aa address access time ____ 25 ____ 35 ____ 55 ns t ace chip enable access time ____ 25 ____ 35 ____ 55 ns t aoe output enable access time ____ 12 ____ 20 ____ 25 ns t oh output hold from address change 3 ____ 3 ____ 3 ____ ns t lz output low-z time (1,2) 0 ____ 0 ____ 0 ____ ns t hz output high-z time (1,2) ____ 12 ____ 15 ____ 30 ns t pu chip enable to power up time (2) 0 ____ 0 ____ 0 ____ ns t pd chip disable to power down time (2) ____ 50 ____ 50 ____ 50 ns 3741 tbl 09
6.42 IDT71V30S/l high-speed 1k x 8 dual-port static ram with interrupts industrial and commercial temperature ranges 6 timing waveform of read cycle no. 1, either side (1) notes: 1. r/ w = v ih , ce = v il , and is oe = v il . address is valid prior to the coincidental with ce transition low. 2. t bdd delay is required only in case where the opposite is port is completing a write operation to same the address location. for si multaneous read operations busy has no relationship to valid output data. 3. start of valid data depends on which timing becomes effective last t aoe , t ace , t aa , and t bdd . timing waveform of read cycle no. 2, either side (3) notes: 1. timing depends on which signal is asserted last, oe or ce . 2. timing depends on which signal is desserted first, oe or ce . 3. r/ w = v ih and the address is valid prior to or coincidental with ce transition low. 4. start of valid data depends on which timing becomes effective last t aoe , t ace , and t bdd . address data out t rc t oh previous data valid t aa t oh data valid 3741 drw 06 t bdd (2,3) busy out ce t ace t aoe t hz t lz t pd valid data t pu 50% oe data out current cc i ss i 50% 3741 drw 07 (4) (1) (1) (2) (2) (4) t lz t hz
6.42 IDT71V30S/l high-speed 1k x 8 dual-port static ram with interrupts industrial and commercial temperature ranges 7 notes: 1. transition is measured 0mv from low- or high-impedance voltage with output test load (figure 2). 2. this parameter is guaranteed by device characterization, but is not production tested. 3. the specification for t dh must be met by the device supplying write data to the sram under all operating conditions. although t dh and t ow values will vary over voltage and temperature, the actual t dh will always be smaller than the actual t ow . 4. 'x' in part number indicates power rating (s or l). 5. industrial temperatures: for specific speeds, packages and powers contact your sales office. ac electrical characteristics over the operating temperature and supply voltage (4,5) symbol parameter 71v30x25 com'l only 71v30x35 com'l & ind 71v30x55 com'l only unit min. max. min. max. min. max. write cycle t wc write cycle time 25 ____ 35 ____ 55 ____ ns t ew chip enable to end-of-write 20 ____ 30 ____ 40 ____ ns t aw address valid to end-of-write 20 ____ 30 ____ 40 ____ ns t as address set-up time 0 ____ 0 ____ 0 ____ ns t wp write pulse width 20 ____ 30 ____ 40 ____ ns t wr write recovery time 0 ____ 0 ____ 0 ____ ns t dw data valid to end-of-write 12 ____ 20 ____ 20 ____ ns t hz output high-z time (1,2) ____ 12 ____ 15 ____ 30 ns t dh data hold time (3) 0 ____ 0 ____ 0 ____ ns t wz write enable to output in high-z (1,2) ____ 15 ____ 15 ____ 30 ns t ow output active from end-of-write (1,2,3) 0 ____ 0 ____ 0 ____ ns 3741 tbl 10
6.42 IDT71V30S/l high-speed 1k x 8 dual-port static ram with interrupts industrial and commercial temperature ranges 8 timing waveform of write cycle no. 2, ce controlled timing (1,5) notes: 1. r/ w or ce must be high during all address transitions. 2. a write occurs during the overlap (t ew or t wp ) of ce = v il and r/ w = v il . 3. t wr is measured from the earlier of ce or r/ w going high to the end of the write cycle. 4. during this period, the l/o pins are in the output state and input signals must not be applied. 5. if the ce low transition occurs simultaneously with or after the r/ w low transition, the outputs remain in the high-impedance state. 6. timing depends on which enable signal ( ce or r/ w ) is asserted last. 7. this parameter is determined be device characterization, but is not production tested. transition is measured 0mv from stead y state with the output test load (figure 2). 8. if oe is low during a r/ w controlled write cycle, the write pulse width must be the larger of t wp or (t wz + t dw ) to allow the i/o drivers to turn off data to be placed on the bus for the required t dw . if oe is high during a r/ w controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t wp . timing waveform of write cycle no. 1,(r/ w controlled timing) (1,5,8) t wc address oe ce r/ w data out data in t as t wr t ow t dw t dh t aw t wp (2) t hz (4) (4) t wz t hz 3741 drw 08 (6) (7) (7) (7) (3) t wc address ce r/ w data in t as t ew t wr t dw t dh t aw 3741 drw 09 (6) (2) (3)
6.42 IDT71V30S/l high-speed 1k x 8 dual-port static ram with interrupts industrial and commercial temperature ranges 9 t wc t wp t dw t dh t bdd t ddd t bda t wdd addr "b" data out "b" data in"a" addr "a" match valid match valid busy "b" 3741 drw 10 (1) t aps r/ w "a" notes: 1. to ensure that the earlier of the two ports wins. 2. ce l = ce r = v il 3. oe = v il for the reading port. 4. all timing is the same for the left and right ports. port 'a' may be either the left or right port. port "b" is opposite from port "a". timing waveform of write with port-to-port read with busy (1,2,3,4) ac electrical characteristics over the operating temperature and supply voltage range (6,7) notes: 1. port-to-port delay through sram cells from writing port to reading port, refer to "timing waveform of write with port-to-port read with busy". 2. to ensure that the earlier of the two ports wins. 3. t bdd is a calculated parameter and is the greater of 0, t wdd ? t wp (actual) or t ddd ? t dw (actual). 4. to ensure that the write cycle is inhibited on port ?b? during contention on port ?a?. 5. to ensure that the write cycle is completed on port ?b? after contention on port ?a?. 6. 'x' in part number indicates power rating (s or l). 7. industrial temperature: for specific speeds, packages and powers contact your sales office. 71v30x25 com'l only 71v30x35 com'l & ind 71v30x55 com'l only unit symbol parameter min. max. min. max. min. max. busy timing (m/s=v ih ) t baa busy access time from address match ____ 20 ____ 20 ____ 30 ns t bda busy disable time from address not matched ____ 20 ____ 20 ____ 30 ns t bac busy access time from chip enable ____ 20 ____ 20 ____ 30 ns t bdc busy disable time from chip enable ____ 20 ____ 20 ____ 30 ns t wh write hold after busy (5) 20 ____ 30 ____ 40 ____ ns t wdd write pulse to data delay (1) ____ 50 ____ 60 ____ 80 ns t ddd write data valid to read data delay (1) ____ 35 ____ 45 ____ 65 ns t aps arbitration priority set-up time (2) 5 ____ 5 ____ 5 ____ ns t bdd busy disable to valid data (3) ____ 30 ____ 30 ____ 45 ns 3741 tbl 11
6.42 IDT71V30S/l high-speed 1k x 8 dual-port static ram with interrupts industrial and commercial temperature ranges 10 notes: 1. t wh must be met for busy . 2. busy is asserted on port 'b' blocking r/ w 'b' , until busy 'b' goes high. 3. all timing is the same for the left and right ports. port 'a' may be either the left or right port. port "b" is opposite from port "a". notes: 1. all timing is the same for left and right ports. port ?a? may be either left or right port. port ?b? is the opposite from por t ?a?. 2. if t aps is not satisified, the busy will be asserted on one side or the other, but there is no guarantee on which side busy will be asserted. timing waveform of busy arbitration controlled address match timing (1) timing waveform of write with busy (3) timing waveform of busy arbitration controlled by ce timing (1) notes: 1. all timing is the same for left and right ports. port ?a? may be either left or right port. port ?b? is the opposite from por t ?a?. 2. if t aps is not satisified, the busy will be asserted on one side or the other, but there is no guarantee on which side busy will be asserted. busy 'b' 3741 drw 11 r/ w 'a' t wp t wh t wb r/ w 'b' (2) (1) , t aps addr 'a' and 'b' addresses match t bac t bdc ce 'b' ce 'a' busy 'a' 3741 drw 12 (2) busy 'b' addresses do not match addresses match t aps addr 'a' addr 'b' t rc or t wc 3741 drw 13 (2) t baa t bda
6.42 IDT71V30S/l high-speed 1k x 8 dual-port static ram with interrupts industrial and commercial temperature ranges 11 int clears timing waveform of interrupt mode (1) int sets notes: . 1. all timing is the same for left and right ports. port ?a? may be either left or right port. port ?b? is the opposite from po rt ?a?. 2. see interrupt truth table ii. 3. timing depends on which enable signal ( ce or r/ w ) is asserted last. 4. timing depends on which enable signal ( ce or r/ w ) is de-asserted first. notes: 1. 'x' in part number indicates power rating (s or l). 2. industrial temperature: for specific speeds, packages and powers contact your sales office. ac electrical characteristics over the operating temperature and supply voltage range (1,2) 71v30x25 com'l only 71v30x35 com'l & ind 71v30x55 com'l only unit symbol parameter min. max. min. max. min. max. interrupt timing t as address set-up time 0 ____ 0 ____ 0 ____ ns t wr write recovery time 0 ____ 0 ____ 0 ____ ns t ins interrupt set time ____ 25 ____ 25 ____ 45 ns t inr interrupt reset time ____ 25 ____ 25 ____ 45 ns 3741 tbl 12 t ins addr 'a' int 'b' interrupt address t wc t as r/ w 'a' t wr 3741 drw 14 (3) (3) (2) (4) t rc interrupt clear address addr 'b' oe 'b' t inr int 'a' 3741 drw 15 t as (3) (3)
6.42 IDT71V30S/l high-speed 1k x 8 dual-port static ram with interrupts industrial and commercial temperature ranges 12 notes : 1. assumes busy l = busy r = v ih 2. if busy l = v il , then no change. 3. if busy r = v il , then no change. 4. 'h' = high,' l' = low,' x' = don?t care notes: 1. pins busy l and busy r are both outputs for idt71v30. busy x outputs on the idt71v30 are non-tristatable push-pull. 2. 'l' if the inputs to the opposite port were stable prior to the address and enable inputs of this port. 'h' if the inputs to the opposite port became stable after the address and enable inputs of this port. if t aps is not met, either busy l or busy r = low will result. busy l and busy r outputs can not be low simultaneously. 3. writes to the left port are internally ignored when busy l outputs are driving low regardless of actual logic level on the pin. writes to the right port are internally ignored when busy r outputs are driving low regardless of actual logic level on the pin. truth tables table i ? non-contention read/write control (4) notes: 1. a 0l ? a 9l a 0r ? a 9r . 2. if busy = l, data is not written. 3. if busy = l, data may not be valid, see t wdd and t ddd timing. 4. 'h' = v ih , 'l' = v il , 'x' = don?t care, 'z' = high impedance table iii ? address busy arbitration table ii ? interrupt flag (1,4) left or right port (1 ) function r/ w ce oe d 0-7 x h x z port disab led and in power-down mode, i sb2 or i sb4 xhx z ce r = ce l = v ih , power-down mode, i sb1 or i sb3 llxdata in data on port written into memory (2 ) hl ldata out data in memory output on port (3) h l h z high impedance outputs 37 41 tb l 13 left port right port function r/ w l ce l oe l a 9l -a 0l int l r/ w r ce r oe r a 9r -a 0r int r llx3ffxxxx x l (2 ) set right int r flag xxxxxxll3ffh (3 ) reset right int r flag xxx x l (3) llx 3fe xset left int l flag xll3feh (2) x x x x x reset left int l flag 3741 tbl 14 inputs outputs function ce l ce r a ol -a 9l a or -a 9r busy l (1) busy r (1) x x no match h h normal h x match h h normal x h match h h normal l l match (2) (2) write inhibit (3) 3741 tbl 15
6.42 IDT71V30S/l high-speed 1k x 8 dual-port static ram with interrupts industrial and commercial temperature ranges 13 functional description the idt71v30 provides two ports with separate control, address and i/o pins that permit independent access for reads or writes to any location in memory. the idt71v30 has an automatic power down feature controlled by ce. the ce controls on-chip power down circuitry that permits the respective port to go into a standby mode when not selected ( ce = v ih ). when a port is enabled, access to the entire memory array is permitted. interrupts if the user chooses the interrupt function, a memory location (mail box or message center) is assigned to each port. the left port interrupt flag ( int l ) is asserted when the right port writes to memory location 3fe (hex), where a write is defined as the ce = r/ w = v il per truth table ii. the left port clears the interrupt by accessing address location 3fe access with ce r = oe r = v il, r/ w is a "don't care". likewise, the right port interrupt flag ( int r ) is asserted when the left port writes to memory location 3ff (hex) and to clear the interrupt flag ( int r ), the right port must access the memory location 3ff. the message (8 bits) at 3fe or 3ff is user-defined, since it is an addressable sram location. if the interrupt function is not used, address locations 3fe and 3ff are not used as mail boxes, and are part of the random access memory. refer to table ii for the interrupt operation. busy logic busy logic provides a hardware indication that both ports of the sram have accessed the same location at the same time. it also allows one of the two accesses to proceed and signals the other side that the sram is ?busy?. the busy pin can then be used to stall the access until the operation on the other side is completed. if a write operation has been attempted from the side that receives a busy indication, the write signal is gated internally to prevent the write from proceeding. the use of busy logic is not required or desirable for all applica- tions. in some cases it may be useful to logically or the busy outputs together and use any busy indication as an interrupt source to flag the event of an illegal or illogical operation.
6.42 IDT71V30S/l high-speed 1k x 8 dual-port static ram with interrupts industrial and commercial temperature ranges 14 ordering information notes: 1. industrial temperature range is available. for specific speeds, packages and powers contact your sales office. 2. green parts available. for specific speeds, packages and powers contact your sales office. a power 99 speed a package a process/ temperature range blank i (1 ) commercial (0 c to +70 c) industrial (-40 c to +85 c) tf 64-pin stqfp (pp64) 3741 drw 20 s l standard power low power 71v30 8k (1k x 8-bit) synchronous dual-port ram speed in nanoseconds commercial only commercial & industrial commercial only xxxxx device type g (2 ) green 25 35 55 tube or tray tape and reel a a blank 8 datasheet document history 12/9/98: initiated datasheet document history converted to new format cosmetic and typographical corrections added additional notes to pin configurations 6/15/99: changed drawing format 8/3/99: page 2 fixed typographical error 9/1/99: removed preliminary 11/12/99: replaced idt logo 1/17/01: pages 1 and 2 moved all of "description" to page 2 and adjusted page layouts page 3 increased storage temperature parameters clarified t a parameter page 4 dc electrical parameters?changed wording from "open" to "disabled" changed 200mv to 0mv in notes 3/14/05: page 1 added green availability to features page 17 added green indicator to ordering information page 1 & 17 replaced old tm logo with new tm logo 7/16/07: page 3 added junction temperature spec values to the absolute maximum rating table added footnote 3 for additional clarification of junction temperature
6.42 IDT71V30S/l high-speed 1k x 8 dual-port static ram with interrupts industrial and commercial temperature ranges 15 the idt logo is a registered trademark of integrated device technology, inc. corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or 408-284-8200 408-284-2794 san jose, ca 95138 fax: 408-284-2775 dualporthelp@idt.com www.idt.com datasheet document history (con't) 10/23/08: page 14 removed "idt" from orderable part number 11/25/09: page 4 in order to correct the dc chars table for the 71v30l35 speed grade and to the data retention chars table, i temp values have been added to each table respectively. in addition, all of the ac tables and the ordering information also now reflect this i temp correction 06/22/15: page 2 removed idt in reference to fabrication page 2 & 14 the package code pp64-1 changed to pp64 to match standard package codes page 14 added tape and reel indicator to ordering information 07/23/15: entire datasheet removed the 55ns industrial speed offering. 55ns speed only offered in commercial grade

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